Relationship between I2C drawn energy / power consumption and data rate











up vote
4
down vote

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Referring to just what the I2C lines draw, am I wrong thinking that the higher the clock frequency the shorter the time there will be (the same amount of) current flowing through the pullups and thus lower power consumed?





side qeustion



I don't think I am going to reach 100 kHz, that's way over the limit of my hardware. I am alternating between about 32 and 4 kHz. Will the same resistor value (3.3k @ 3V) be good for both?










share|improve this question




























    up vote
    4
    down vote

    favorite












    Referring to just what the I2C lines draw, am I wrong thinking that the higher the clock frequency the shorter the time there will be (the same amount of) current flowing through the pullups and thus lower power consumed?





    side qeustion



    I don't think I am going to reach 100 kHz, that's way over the limit of my hardware. I am alternating between about 32 and 4 kHz. Will the same resistor value (3.3k @ 3V) be good for both?










    share|improve this question


























      up vote
      4
      down vote

      favorite









      up vote
      4
      down vote

      favorite











      Referring to just what the I2C lines draw, am I wrong thinking that the higher the clock frequency the shorter the time there will be (the same amount of) current flowing through the pullups and thus lower power consumed?





      side qeustion



      I don't think I am going to reach 100 kHz, that's way over the limit of my hardware. I am alternating between about 32 and 4 kHz. Will the same resistor value (3.3k @ 3V) be good for both?










      share|improve this question















      Referring to just what the I2C lines draw, am I wrong thinking that the higher the clock frequency the shorter the time there will be (the same amount of) current flowing through the pullups and thus lower power consumed?





      side qeustion



      I don't think I am going to reach 100 kHz, that's way over the limit of my hardware. I am alternating between about 32 and 4 kHz. Will the same resistor value (3.3k @ 3V) be good for both?







      i2c frequency energy power-consumption clock-speed






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      share|improve this question













      share|improve this question




      share|improve this question








      edited yesterday









      Michel Keijzers

      5,47062360




      5,47062360










      asked yesterday









      kellogs

      34017




      34017






















          4 Answers
          4






          active

          oldest

          votes

















          up vote
          5
          down vote



          accepted










          Higher clock frequency usually require lower pull-up value, thus increasing the current.



          Increasing the clock frequency from 100kHz to 400kHz usually requires the pull-up to be reduced with a factor of 4-5.



          Since the power is inverse proportional to the resistance the power consumed will be almost the same.






          share|improve this answer





















          • How about my side question ?
            – kellogs
            yesterday






          • 4




            @kellogs 32KHz is really slow for I2C. Depending on the capacity of the bus you can probably use 10k or more. Use a scope to see the rising edge of SCL and SDA to determine the value of the pull-up. SDA must be able to rise from low to high in the low period of SCL.
            – Peter Karlsen
            yesterday


















          up vote
          7
          down vote













          The I2C data and clock lines draw power when they get pulled low. Because then power is sunk through the pull-up resistors.



          While a line is pulled low it will draw 5V/4.7k$~Omega approx$ 1mA. Assuming 5V VCC and 4.7k pullup resistors.



          The clock line will have a 50% duty cycle. The data line is low at least 1 out of every 9 clock cycles (every ack for a successful byte) but you are rarely going to send/receive only 0xff bytes. It's more likely going to be pulled low 75% of the time.



          But indeed faster clock means shorter transmission which means less power lost through the pull-ups. However faster transmission may require lower value resistors to overcome the parasitic capacitance between the lines and ground.






          share|improve this answer





















          • It also takes energy to charge and discharge the parasitic capacitance. I think another factor that affects power consumption is active time percentage of the bus.
            – Long Pham
            yesterday










          • How about my side question ?
            – kellogs
            yesterday










          • The power drawn charging and discharging the capacitance would (assuming you do not change the circuit and that your clock is slow enough for this happen to effective completion) be determined by the number of clock cycles but not by the clock rate.
            – Chris Stratton
            yesterday










          • I'm curious about the 75% of the time value. I would have said about 50% (or better 56, including the ack), since all the values are equally probable. 75% means that the average number of zeros per byte is between 5 or 6; was yours a pessimistic estimation or 75% is the actual statistical value?
            – frarugi87
            yesterday






          • 2




            @frarugi87 pessimistic estimation. Based on the habit of using low numbers for addresses of various control registers and the values they take. So I guestimated that the top 3 bits are very often just 0.
            – ratchet freak
            yesterday


















          up vote
          6
          down vote













          Your thinking is correct, as long as you can achieve a higher speed with the same pull up resistors.






          share|improve this answer





















          • How about my side question ?
            – kellogs
            yesterday






          • 3




            @kellogs cannot answer that as I have no idea what your lines capacitance is. So I can only tell you that we are running 100 kHz with 100 kOhm resistors in one of our products with no problems. I would guess that you are fine.
            – Arsenal
            yesterday






          • 1




            any way to guesstimate it ?
            – kellogs
            yesterday






          • 3




            @kellogs well, 10 pF for any pin connected to the bus, 50 pF per meter for the length of the line would be a conservative guess I think. If your I²C bus is on a single PCB I have a hard time to imagine why it wouldn't work with 3k3 pull up resistors.
            – Arsenal
            yesterday


















          up vote
          2
          down vote













          As @ratchet-freak stated, In terms of time, you could have 75% of the time the bus pulled-down, hence, if you increase the clock rate, your consumption by the bus will decrease as long as you have the same value for pull-up resistors. But, at higher speeds, resistor values should be reduced.



          Having this, the consumption of the bus will be lower, but slaves and masters devices could increase their consumption depending on the clock rate.



          Regarding your side question, if 3.3kohms suits both 4khz and 32khz, you have to check the capacitance of your bus. This capacitance depends on the length of the bus, the distance between lines and the number of devices attached to it. It could be difficult to calculate the real capacitance, but you can check the waveform of your data in the bus at both frequencies and see if there is any distortion of the signal at 32khz using 3.3k.






          share|improve this answer























          • How about my side question ?
            – kellogs
            yesterday











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          4 Answers
          4






          active

          oldest

          votes








          4 Answers
          4






          active

          oldest

          votes









          active

          oldest

          votes






          active

          oldest

          votes








          up vote
          5
          down vote



          accepted










          Higher clock frequency usually require lower pull-up value, thus increasing the current.



          Increasing the clock frequency from 100kHz to 400kHz usually requires the pull-up to be reduced with a factor of 4-5.



          Since the power is inverse proportional to the resistance the power consumed will be almost the same.






          share|improve this answer





















          • How about my side question ?
            – kellogs
            yesterday






          • 4




            @kellogs 32KHz is really slow for I2C. Depending on the capacity of the bus you can probably use 10k or more. Use a scope to see the rising edge of SCL and SDA to determine the value of the pull-up. SDA must be able to rise from low to high in the low period of SCL.
            – Peter Karlsen
            yesterday















          up vote
          5
          down vote



          accepted










          Higher clock frequency usually require lower pull-up value, thus increasing the current.



          Increasing the clock frequency from 100kHz to 400kHz usually requires the pull-up to be reduced with a factor of 4-5.



          Since the power is inverse proportional to the resistance the power consumed will be almost the same.






          share|improve this answer





















          • How about my side question ?
            – kellogs
            yesterday






          • 4




            @kellogs 32KHz is really slow for I2C. Depending on the capacity of the bus you can probably use 10k or more. Use a scope to see the rising edge of SCL and SDA to determine the value of the pull-up. SDA must be able to rise from low to high in the low period of SCL.
            – Peter Karlsen
            yesterday













          up vote
          5
          down vote



          accepted







          up vote
          5
          down vote



          accepted






          Higher clock frequency usually require lower pull-up value, thus increasing the current.



          Increasing the clock frequency from 100kHz to 400kHz usually requires the pull-up to be reduced with a factor of 4-5.



          Since the power is inverse proportional to the resistance the power consumed will be almost the same.






          share|improve this answer












          Higher clock frequency usually require lower pull-up value, thus increasing the current.



          Increasing the clock frequency from 100kHz to 400kHz usually requires the pull-up to be reduced with a factor of 4-5.



          Since the power is inverse proportional to the resistance the power consumed will be almost the same.







          share|improve this answer












          share|improve this answer



          share|improve this answer










          answered yesterday









          Peter Karlsen

          49628




          49628












          • How about my side question ?
            – kellogs
            yesterday






          • 4




            @kellogs 32KHz is really slow for I2C. Depending on the capacity of the bus you can probably use 10k or more. Use a scope to see the rising edge of SCL and SDA to determine the value of the pull-up. SDA must be able to rise from low to high in the low period of SCL.
            – Peter Karlsen
            yesterday


















          • How about my side question ?
            – kellogs
            yesterday






          • 4




            @kellogs 32KHz is really slow for I2C. Depending on the capacity of the bus you can probably use 10k or more. Use a scope to see the rising edge of SCL and SDA to determine the value of the pull-up. SDA must be able to rise from low to high in the low period of SCL.
            – Peter Karlsen
            yesterday
















          How about my side question ?
          – kellogs
          yesterday




          How about my side question ?
          – kellogs
          yesterday




          4




          4




          @kellogs 32KHz is really slow for I2C. Depending on the capacity of the bus you can probably use 10k or more. Use a scope to see the rising edge of SCL and SDA to determine the value of the pull-up. SDA must be able to rise from low to high in the low period of SCL.
          – Peter Karlsen
          yesterday




          @kellogs 32KHz is really slow for I2C. Depending on the capacity of the bus you can probably use 10k or more. Use a scope to see the rising edge of SCL and SDA to determine the value of the pull-up. SDA must be able to rise from low to high in the low period of SCL.
          – Peter Karlsen
          yesterday












          up vote
          7
          down vote













          The I2C data and clock lines draw power when they get pulled low. Because then power is sunk through the pull-up resistors.



          While a line is pulled low it will draw 5V/4.7k$~Omega approx$ 1mA. Assuming 5V VCC and 4.7k pullup resistors.



          The clock line will have a 50% duty cycle. The data line is low at least 1 out of every 9 clock cycles (every ack for a successful byte) but you are rarely going to send/receive only 0xff bytes. It's more likely going to be pulled low 75% of the time.



          But indeed faster clock means shorter transmission which means less power lost through the pull-ups. However faster transmission may require lower value resistors to overcome the parasitic capacitance between the lines and ground.






          share|improve this answer





















          • It also takes energy to charge and discharge the parasitic capacitance. I think another factor that affects power consumption is active time percentage of the bus.
            – Long Pham
            yesterday










          • How about my side question ?
            – kellogs
            yesterday










          • The power drawn charging and discharging the capacitance would (assuming you do not change the circuit and that your clock is slow enough for this happen to effective completion) be determined by the number of clock cycles but not by the clock rate.
            – Chris Stratton
            yesterday










          • I'm curious about the 75% of the time value. I would have said about 50% (or better 56, including the ack), since all the values are equally probable. 75% means that the average number of zeros per byte is between 5 or 6; was yours a pessimistic estimation or 75% is the actual statistical value?
            – frarugi87
            yesterday






          • 2




            @frarugi87 pessimistic estimation. Based on the habit of using low numbers for addresses of various control registers and the values they take. So I guestimated that the top 3 bits are very often just 0.
            – ratchet freak
            yesterday















          up vote
          7
          down vote













          The I2C data and clock lines draw power when they get pulled low. Because then power is sunk through the pull-up resistors.



          While a line is pulled low it will draw 5V/4.7k$~Omega approx$ 1mA. Assuming 5V VCC and 4.7k pullup resistors.



          The clock line will have a 50% duty cycle. The data line is low at least 1 out of every 9 clock cycles (every ack for a successful byte) but you are rarely going to send/receive only 0xff bytes. It's more likely going to be pulled low 75% of the time.



          But indeed faster clock means shorter transmission which means less power lost through the pull-ups. However faster transmission may require lower value resistors to overcome the parasitic capacitance between the lines and ground.






          share|improve this answer





















          • It also takes energy to charge and discharge the parasitic capacitance. I think another factor that affects power consumption is active time percentage of the bus.
            – Long Pham
            yesterday










          • How about my side question ?
            – kellogs
            yesterday










          • The power drawn charging and discharging the capacitance would (assuming you do not change the circuit and that your clock is slow enough for this happen to effective completion) be determined by the number of clock cycles but not by the clock rate.
            – Chris Stratton
            yesterday










          • I'm curious about the 75% of the time value. I would have said about 50% (or better 56, including the ack), since all the values are equally probable. 75% means that the average number of zeros per byte is between 5 or 6; was yours a pessimistic estimation or 75% is the actual statistical value?
            – frarugi87
            yesterday






          • 2




            @frarugi87 pessimistic estimation. Based on the habit of using low numbers for addresses of various control registers and the values they take. So I guestimated that the top 3 bits are very often just 0.
            – ratchet freak
            yesterday













          up vote
          7
          down vote










          up vote
          7
          down vote









          The I2C data and clock lines draw power when they get pulled low. Because then power is sunk through the pull-up resistors.



          While a line is pulled low it will draw 5V/4.7k$~Omega approx$ 1mA. Assuming 5V VCC and 4.7k pullup resistors.



          The clock line will have a 50% duty cycle. The data line is low at least 1 out of every 9 clock cycles (every ack for a successful byte) but you are rarely going to send/receive only 0xff bytes. It's more likely going to be pulled low 75% of the time.



          But indeed faster clock means shorter transmission which means less power lost through the pull-ups. However faster transmission may require lower value resistors to overcome the parasitic capacitance between the lines and ground.






          share|improve this answer












          The I2C data and clock lines draw power when they get pulled low. Because then power is sunk through the pull-up resistors.



          While a line is pulled low it will draw 5V/4.7k$~Omega approx$ 1mA. Assuming 5V VCC and 4.7k pullup resistors.



          The clock line will have a 50% duty cycle. The data line is low at least 1 out of every 9 clock cycles (every ack for a successful byte) but you are rarely going to send/receive only 0xff bytes. It's more likely going to be pulled low 75% of the time.



          But indeed faster clock means shorter transmission which means less power lost through the pull-ups. However faster transmission may require lower value resistors to overcome the parasitic capacitance between the lines and ground.







          share|improve this answer












          share|improve this answer



          share|improve this answer










          answered yesterday









          ratchet freak

          2,5301011




          2,5301011












          • It also takes energy to charge and discharge the parasitic capacitance. I think another factor that affects power consumption is active time percentage of the bus.
            – Long Pham
            yesterday










          • How about my side question ?
            – kellogs
            yesterday










          • The power drawn charging and discharging the capacitance would (assuming you do not change the circuit and that your clock is slow enough for this happen to effective completion) be determined by the number of clock cycles but not by the clock rate.
            – Chris Stratton
            yesterday










          • I'm curious about the 75% of the time value. I would have said about 50% (or better 56, including the ack), since all the values are equally probable. 75% means that the average number of zeros per byte is between 5 or 6; was yours a pessimistic estimation or 75% is the actual statistical value?
            – frarugi87
            yesterday






          • 2




            @frarugi87 pessimistic estimation. Based on the habit of using low numbers for addresses of various control registers and the values they take. So I guestimated that the top 3 bits are very often just 0.
            – ratchet freak
            yesterday


















          • It also takes energy to charge and discharge the parasitic capacitance. I think another factor that affects power consumption is active time percentage of the bus.
            – Long Pham
            yesterday










          • How about my side question ?
            – kellogs
            yesterday










          • The power drawn charging and discharging the capacitance would (assuming you do not change the circuit and that your clock is slow enough for this happen to effective completion) be determined by the number of clock cycles but not by the clock rate.
            – Chris Stratton
            yesterday










          • I'm curious about the 75% of the time value. I would have said about 50% (or better 56, including the ack), since all the values are equally probable. 75% means that the average number of zeros per byte is between 5 or 6; was yours a pessimistic estimation or 75% is the actual statistical value?
            – frarugi87
            yesterday






          • 2




            @frarugi87 pessimistic estimation. Based on the habit of using low numbers for addresses of various control registers and the values they take. So I guestimated that the top 3 bits are very often just 0.
            – ratchet freak
            yesterday
















          It also takes energy to charge and discharge the parasitic capacitance. I think another factor that affects power consumption is active time percentage of the bus.
          – Long Pham
          yesterday




          It also takes energy to charge and discharge the parasitic capacitance. I think another factor that affects power consumption is active time percentage of the bus.
          – Long Pham
          yesterday












          How about my side question ?
          – kellogs
          yesterday




          How about my side question ?
          – kellogs
          yesterday












          The power drawn charging and discharging the capacitance would (assuming you do not change the circuit and that your clock is slow enough for this happen to effective completion) be determined by the number of clock cycles but not by the clock rate.
          – Chris Stratton
          yesterday




          The power drawn charging and discharging the capacitance would (assuming you do not change the circuit and that your clock is slow enough for this happen to effective completion) be determined by the number of clock cycles but not by the clock rate.
          – Chris Stratton
          yesterday












          I'm curious about the 75% of the time value. I would have said about 50% (or better 56, including the ack), since all the values are equally probable. 75% means that the average number of zeros per byte is between 5 or 6; was yours a pessimistic estimation or 75% is the actual statistical value?
          – frarugi87
          yesterday




          I'm curious about the 75% of the time value. I would have said about 50% (or better 56, including the ack), since all the values are equally probable. 75% means that the average number of zeros per byte is between 5 or 6; was yours a pessimistic estimation or 75% is the actual statistical value?
          – frarugi87
          yesterday




          2




          2




          @frarugi87 pessimistic estimation. Based on the habit of using low numbers for addresses of various control registers and the values they take. So I guestimated that the top 3 bits are very often just 0.
          – ratchet freak
          yesterday




          @frarugi87 pessimistic estimation. Based on the habit of using low numbers for addresses of various control registers and the values they take. So I guestimated that the top 3 bits are very often just 0.
          – ratchet freak
          yesterday










          up vote
          6
          down vote













          Your thinking is correct, as long as you can achieve a higher speed with the same pull up resistors.






          share|improve this answer





















          • How about my side question ?
            – kellogs
            yesterday






          • 3




            @kellogs cannot answer that as I have no idea what your lines capacitance is. So I can only tell you that we are running 100 kHz with 100 kOhm resistors in one of our products with no problems. I would guess that you are fine.
            – Arsenal
            yesterday






          • 1




            any way to guesstimate it ?
            – kellogs
            yesterday






          • 3




            @kellogs well, 10 pF for any pin connected to the bus, 50 pF per meter for the length of the line would be a conservative guess I think. If your I²C bus is on a single PCB I have a hard time to imagine why it wouldn't work with 3k3 pull up resistors.
            – Arsenal
            yesterday















          up vote
          6
          down vote













          Your thinking is correct, as long as you can achieve a higher speed with the same pull up resistors.






          share|improve this answer





















          • How about my side question ?
            – kellogs
            yesterday






          • 3




            @kellogs cannot answer that as I have no idea what your lines capacitance is. So I can only tell you that we are running 100 kHz with 100 kOhm resistors in one of our products with no problems. I would guess that you are fine.
            – Arsenal
            yesterday






          • 1




            any way to guesstimate it ?
            – kellogs
            yesterday






          • 3




            @kellogs well, 10 pF for any pin connected to the bus, 50 pF per meter for the length of the line would be a conservative guess I think. If your I²C bus is on a single PCB I have a hard time to imagine why it wouldn't work with 3k3 pull up resistors.
            – Arsenal
            yesterday













          up vote
          6
          down vote










          up vote
          6
          down vote









          Your thinking is correct, as long as you can achieve a higher speed with the same pull up resistors.






          share|improve this answer












          Your thinking is correct, as long as you can achieve a higher speed with the same pull up resistors.







          share|improve this answer












          share|improve this answer



          share|improve this answer










          answered yesterday









          Arsenal

          12.1k11240




          12.1k11240












          • How about my side question ?
            – kellogs
            yesterday






          • 3




            @kellogs cannot answer that as I have no idea what your lines capacitance is. So I can only tell you that we are running 100 kHz with 100 kOhm resistors in one of our products with no problems. I would guess that you are fine.
            – Arsenal
            yesterday






          • 1




            any way to guesstimate it ?
            – kellogs
            yesterday






          • 3




            @kellogs well, 10 pF for any pin connected to the bus, 50 pF per meter for the length of the line would be a conservative guess I think. If your I²C bus is on a single PCB I have a hard time to imagine why it wouldn't work with 3k3 pull up resistors.
            – Arsenal
            yesterday


















          • How about my side question ?
            – kellogs
            yesterday






          • 3




            @kellogs cannot answer that as I have no idea what your lines capacitance is. So I can only tell you that we are running 100 kHz with 100 kOhm resistors in one of our products with no problems. I would guess that you are fine.
            – Arsenal
            yesterday






          • 1




            any way to guesstimate it ?
            – kellogs
            yesterday






          • 3




            @kellogs well, 10 pF for any pin connected to the bus, 50 pF per meter for the length of the line would be a conservative guess I think. If your I²C bus is on a single PCB I have a hard time to imagine why it wouldn't work with 3k3 pull up resistors.
            – Arsenal
            yesterday
















          How about my side question ?
          – kellogs
          yesterday




          How about my side question ?
          – kellogs
          yesterday




          3




          3




          @kellogs cannot answer that as I have no idea what your lines capacitance is. So I can only tell you that we are running 100 kHz with 100 kOhm resistors in one of our products with no problems. I would guess that you are fine.
          – Arsenal
          yesterday




          @kellogs cannot answer that as I have no idea what your lines capacitance is. So I can only tell you that we are running 100 kHz with 100 kOhm resistors in one of our products with no problems. I would guess that you are fine.
          – Arsenal
          yesterday




          1




          1




          any way to guesstimate it ?
          – kellogs
          yesterday




          any way to guesstimate it ?
          – kellogs
          yesterday




          3




          3




          @kellogs well, 10 pF for any pin connected to the bus, 50 pF per meter for the length of the line would be a conservative guess I think. If your I²C bus is on a single PCB I have a hard time to imagine why it wouldn't work with 3k3 pull up resistors.
          – Arsenal
          yesterday




          @kellogs well, 10 pF for any pin connected to the bus, 50 pF per meter for the length of the line would be a conservative guess I think. If your I²C bus is on a single PCB I have a hard time to imagine why it wouldn't work with 3k3 pull up resistors.
          – Arsenal
          yesterday










          up vote
          2
          down vote













          As @ratchet-freak stated, In terms of time, you could have 75% of the time the bus pulled-down, hence, if you increase the clock rate, your consumption by the bus will decrease as long as you have the same value for pull-up resistors. But, at higher speeds, resistor values should be reduced.



          Having this, the consumption of the bus will be lower, but slaves and masters devices could increase their consumption depending on the clock rate.



          Regarding your side question, if 3.3kohms suits both 4khz and 32khz, you have to check the capacitance of your bus. This capacitance depends on the length of the bus, the distance between lines and the number of devices attached to it. It could be difficult to calculate the real capacitance, but you can check the waveform of your data in the bus at both frequencies and see if there is any distortion of the signal at 32khz using 3.3k.






          share|improve this answer























          • How about my side question ?
            – kellogs
            yesterday















          up vote
          2
          down vote













          As @ratchet-freak stated, In terms of time, you could have 75% of the time the bus pulled-down, hence, if you increase the clock rate, your consumption by the bus will decrease as long as you have the same value for pull-up resistors. But, at higher speeds, resistor values should be reduced.



          Having this, the consumption of the bus will be lower, but slaves and masters devices could increase their consumption depending on the clock rate.



          Regarding your side question, if 3.3kohms suits both 4khz and 32khz, you have to check the capacitance of your bus. This capacitance depends on the length of the bus, the distance between lines and the number of devices attached to it. It could be difficult to calculate the real capacitance, but you can check the waveform of your data in the bus at both frequencies and see if there is any distortion of the signal at 32khz using 3.3k.






          share|improve this answer























          • How about my side question ?
            – kellogs
            yesterday













          up vote
          2
          down vote










          up vote
          2
          down vote









          As @ratchet-freak stated, In terms of time, you could have 75% of the time the bus pulled-down, hence, if you increase the clock rate, your consumption by the bus will decrease as long as you have the same value for pull-up resistors. But, at higher speeds, resistor values should be reduced.



          Having this, the consumption of the bus will be lower, but slaves and masters devices could increase their consumption depending on the clock rate.



          Regarding your side question, if 3.3kohms suits both 4khz and 32khz, you have to check the capacitance of your bus. This capacitance depends on the length of the bus, the distance between lines and the number of devices attached to it. It could be difficult to calculate the real capacitance, but you can check the waveform of your data in the bus at both frequencies and see if there is any distortion of the signal at 32khz using 3.3k.






          share|improve this answer














          As @ratchet-freak stated, In terms of time, you could have 75% of the time the bus pulled-down, hence, if you increase the clock rate, your consumption by the bus will decrease as long as you have the same value for pull-up resistors. But, at higher speeds, resistor values should be reduced.



          Having this, the consumption of the bus will be lower, but slaves and masters devices could increase their consumption depending on the clock rate.



          Regarding your side question, if 3.3kohms suits both 4khz and 32khz, you have to check the capacitance of your bus. This capacitance depends on the length of the bus, the distance between lines and the number of devices attached to it. It could be difficult to calculate the real capacitance, but you can check the waveform of your data in the bus at both frequencies and see if there is any distortion of the signal at 32khz using 3.3k.







          share|improve this answer














          share|improve this answer



          share|improve this answer








          edited yesterday

























          answered yesterday









          gustavovelascoh

          1856




          1856












          • How about my side question ?
            – kellogs
            yesterday


















          • How about my side question ?
            – kellogs
            yesterday
















          How about my side question ?
          – kellogs
          yesterday




          How about my side question ?
          – kellogs
          yesterday


















           

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